module sim(clk, high_life, border,i,j, cycle, mem_row, mem_col, mem_we, world_out, world_in,out);
input clk; // semnalul de ceas
input high_life; // 0 - daca se folosesc regulile B3/S23, 1 daca se folosesc regulile B36/S23
input border; // 0 - daca lumea este ciclica, 1 - daca lumea este marginita cu 0
output cycle; // indica momentul în care s-a terminat simularea unui ciclu
output [3:0] mem_row; // indica rândul celulei active
output [5:0] mem_col; // indica coloana celului active
output mem_we; // indica daca celula activa va fi scrisa cu valoarea din "world_in"
input world_out; // 0 - celula activa este moarta, 1 - celula activa este vie
output world_in; // indica noua valoare care va fi scrisa în celula activa
output out;
reg out;
input [15:0] i;
input [63:0] j;
reg [63:0] data [15:0];
parameter row=16;
parameter col=63;
initial begin
high_life =0;
border=1;
data[15] = 64'b0000000000000000000000000000000000000000000000000000000000000000;
data[14] = 64'b0000010000000000000000000000000000000000000000000000000000000000;
data[13] = 64'b0000001000000000000000000000000000000000000000000000000000000000;
data[12] = 64'b0000111000000000000000000000000000000000000000000000000000000000;
data[11] = 64'b0000000000000000000000000000000000000000000000000000000000000000;
data[10] = 64'b0000000000000000000000000000000000000000000000000000000000000000;
data[ 9] = 64'b0000000000000000000000000000000000000000000000000000000000000000;
data[ 8] = 64'b0000000000000000000000000000000000000000000000000000000000000000;
data[ 7] = 64'b0000000000000000000000000000000000000000000000000000000000000000;
data[ 6] = 64'b0000000000000000000000000000000000000000000000000000000000000000;
data[ 5] = 64'b0000000000000000000000000000000000000000000000000000000000000000;
data[ 4] = 64'b0000000000000000000000000000000000000000000000000000000000000000;
data[ 3] = 64'b0000000000000000000000000000000000000000000000000000000000000000;
data[ 2] = 64'b0000000000000000000000000000000000000000000000000000000000000000;
data[ 1] = 64'b0000000000000000000000000000000000000000000000000000000000000000;
data[ 0] = 64'b0000000000000000000000000000000000000000000000000000000000000000;
end
always @(posedge clk)
begin
for(i=1;i<row;i=i+1)
for(j=1;j<col;j=j+1)
begin
data[i]=data[j]+data[j+1]+data[j+2];
if(data[i]==3)
begin
data[mem_row][mem_col]<=data[i][j];
data[mem_row][mem_col]<=data[i][j+1];
data[mem_row][mem_col]<=data[i][j+2];
end
else
if(data[i]!=3)
begin
data[i][j]=1'b0;
data[i][j+1]=1'b0;
data[i][j+2]=1'b0;
end
end
end
always @(posedge clk)
begin
for(j=1;j<col;j=j+1)
for(i=1;i<row;i=i+1)
begin
data[j]=data[i]+data[i+1]+data[i+2];
if(data[j]==3)
begin
data[mem_row][mem-col]<=data[i][j];
data[mem_row][mem_col]<=data[i+1][j];
data[mem_row][mem_col]<=data[i+2][j];
end
else
if(data[j]!=3)
begin
data[i][j]=1'b0;
data[i+1][j]=1'b0;
data[i+2][j]=1'b0;
end
end
end.
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